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silan semiconductors SC88E43 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2000.12.31 1 extended voltage calling number identification circuit 2 description the SC88E43 calling number identification circuit 2(ecnic2) is a low power cmos integrated circuit intended for receiving physical layer signals transmitted according to bt (british telecom) sin227 & sin242, the u.k.s cca (cable communications association) tw/p&e/312 and bellcore gr-30-core & sr-tsv-002476 specifications. the SC88E43 is suitable for applications using a fixed voltage power source between 3 and 5v 10%. features * compatible with: -- british telecom (bt) sin227 & sin242 -- u.k.s cable communications association (cca) specification tw/p&e/312 -- bellcore gr-30-core (formerly known as tr-nwt-000030) & sr-tsv-002476 * bellcore cpe alerting signal (cas) and bt idle state tone alert signal detection * ring and line reversal detection * 1200 baud bell 202 and ccitt v.23 frequency shift keying (fsk) demodulation * 3 or 5v 10% supply voltage * high input sensitivity (-40dbv tone and fsk detection) * selectable 3-wire fsk data interface (microcontroller or SC88E43 controlled) * low power cmos with powerdown mode * input gain adjustable amplifier * carrier detect status output * uses 3.58 mhz crystal sop-24 dip-24 applications * bt calling line identity presentation (clip), cca clip, and bellcore calling identity delivery (cid) systems * feature phones, including analog display services interface (adsi) phones * phone set adjunct boxes * fax and answering machines * database query and computer telephony integration (cti) systems ordering information SC88E43s 24 pin dip SC88E43 24 pin soic recommended operating conditions (ta=25 c ; voltages are with respect to v ss ) parameter symbol min typ max unit power supplies v dd 2.7 -- 5.5 v clock frequency f osc -- 3.579545 -- mhz tolerance on clock frequency d f c -0.1 -- +0.1 % operating temperature t op -40 -- 85 c
silan semiconductors SC88E43 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2000.12.31 2 pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 in+ in- gs vref cap mode osci osco vss vdd st/gt est std data dclk fsken pwdn ic SC88E43 trigin trigrc trigout dr cd int block diagram tone detection algorithm alert signal high tone filter alert signal low tone filter bias generator oscillator anti-alias filter fsk bandpass filter fsk demodulator data timing recovery carrier detector interrupt generator guard time 1 2 3 4 5 14 10 11 6 7 8 24 12 22 23 21 19 20 18 16 17 9 15 in+ in- gs vref cap pwdn oscin oscout trigin trigrc trigout vss vdd est st/gt std int cd dr data dclk mode fsken + - to internal cct. to internal cct.
silan semiconductors SC88E43 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2000.12.31 3 absolute maximum ratings (voltages are with respect to vss, unless otherwise stated). characteristic symbol value unit supply voltage v dd -0.3 ~ 6.0 v voltage on any pin other than supplies* v pin vss-0.3v ~ v dd +0.3v v current at any pin other than supplies i pin 10 ma storage temperature tstg -65 ~ +150 c * under normal operating conditions voltage on any pin except supplies can be minimum v ss -1v to maximum v dd +1v for an input current limited to less than 20 0 ma. dc electrical characteristics parameter symbol test conditions min typ max unit stand-by supply current i ddq all input are v dd /v ss except for oscillator pins. no analog input. outputs unloaded. pwdn = v dd. -- 0.5 15 m a v dd =5v 10% -- 4.7 8 ma operating supply current v dd =3v 10% i dd all input are v dd /v ss except for oscillator pins. no analog input. outputs unloaded. pwdn = v ss; fsken = v dd. -- 2.5 4.5 ma power consumption p o -- -- -- 44 mw schmitt input high threshold v t+ trigin, trigrc ,pwdn pins 0.48v dd -- 0.68v dd v schmitt input low threshold v t- trigin, trigrc ,pwdn pins 0.28v dd -- 0.48v dd v schmitt hysteresis v hys trigin, trigrc ,pwdn pins 0.2 -- -- v cmos input high voltage v ih dclk,mode,fsken pins 0.7v dd -- v dd v cmos input low voltage v il dclk,mode,fsken pins v ss -- 0.3v dd v output high sourcing current i oh v oh =0.9v dd trigout ,dclk,dada, dr , cd ,std,est,st/gt pins 0.8 -- -- ma output low sinking current i ol v ol =0.1v dd trigout ,dclk,data, dr , cd , std, est,st/gt, trigrc int pins 2----ma i in1 v in =v dd to v ss in+,in-,trigin pins -- -- 1 m a input current i in2 v in =v dd to v ss pwdn,dclk,mode,fsken -- -- 10 m a (to be continued)
silan semiconductors SC88E43 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2000.12.31 4 (continued) parameter symbol test conditions min typ max unit i oz1 v out =v dd to v ss, trigrc pin. -- -- 1 m a i oz2 v out =v dd to v ss, int pin. -- -- 10 m a output high-impedance current i oz3 v out =v dd to v ss, st/gt pin. -- -- 5 m a output voltage v ref no load. vref pin 0.5v dd -0.05 -- 0.5v dd +0.05 v output resistance r ref vref pin -- 2 k w comparator threshold voltage v tgt st/gt pin 0.5v dd - 0.05 -- 0.5v dd +0.05 v ac electrical characteristics parameter symbol conditions min typ max unit notes dual tone alert signal detection low tone frequency f l -- 2130 -- hz high tone frequency f h -- 2750 -- hz frequency deviation accept 1.1% -- -- -- 4 frequency deviation reject 3.5% -- -- -- 5 -40 -- -2 dbv a accept signal level per tone -37.78 -- 0.22 dbm b 3 -- -- -46 dbv rejet signal level per tone -- -- -43.78 dbm 3 positive and negtive twist accept 7---- db c signal to noise ratio snr tone 20 -- -- db 1,2 timming parameter measurement voltage levels cmos threshold voltage v ct -- 0.5v dd -- v rise/fall threshold voltage high v hm -- 0.7v dd -- v rise/fall threshold voltage low v lm -- 0.3v dd -- v gain setting amplifier input leakage current i in v ss v in v dd -- -- 1 m a input resistance r in -- 10 -- -- m w input offset voltage v os -- -- -- 25 mv power supply rejection ratio psrr 1khz ripple on v dd 40 -- -- db (to be continued)
silan semiconductors SC88E43 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2000.12.31 5 (continued) parameter symbol conditions min typ max unit notes common mode rejection cmrr v cmmin v in v cmmax 40 -- -- db dc open loop voltage gain a vol -- 30 -- -- db unity gain bandwidth f c -- 0.3 -- -- mhz output voltage swing v o load 3 50k w 0.5 -- v dd -0.5 v pp maximum capacitive load (gs) c l -- -- -- 100 pf maximum resistive load (gs) r l -- 50 -- -- k w common mode range voltage v cm -- 1.0 -- v dd -0.1 v fsk detection -- -40 -- -8 dbv a -- -37.78 -- -5.78 dbm b input detection level -- 10 -- 398.1 mvrms 6,8 transmission rate -- 1188 1200 1212 baud bell 202 1 (mark) 1188 1200 1212 hz bell 202 0 (space) 2178 2200 2222 hz ccitt v.23 1 (mark) 1280.5 1300 1319.5 hz input frequency detection ccitt v.23 0 (space) 2068.5 2100 2131.5 hz signal to noise ratio snr fsk -- 20 -- -- db 6,7 dual tone alert signal timing alert signal present detect time t dp -- 0.5 -- 10 ms 9 alert signal absent detect time t da -- 0.1 -- 8 ms 9 3-wire interface timming power-up time t pu -- -- 50 ms power-down time t pd pwdn, osc1 pins -- -- 1 ms input fsk to cd low delay t cp -- -- 25 ms input fsk to cd high delay t ca 8---- ms hysteresis cd pin 8----ms 3-wire interface timming (mode 0) risetime t rr dr pin -- -- 200 ns 10 fall time t rf dr pin -- -- 200 ns 10 low time trl dr pin 415 416 417 m s 12 rate -- data pin 1188 1200 1212 baud 11 input fsk to data delay t idd data pin -- 1 5 ms (to be continued)
silan semiconductors SC88E43 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2000.12.31 6 (continued) parameter symbol conditions min typ max unit notes rise time t r -- -- 200 ns 10 fall time t f -- -- 200 ns 10 data to dclk delay t dcd 6 416 -- m s 11,12, 13 dclk to data delay t cdd data, dclk pins 6 416 -- m s 11,12, 13 frequency f dclk0 1201.6 1202.8 1204 hz 12 high time t ch 415 416 417 m s 12 low time t cl dclk pin 415 416 417 m s 12 dclk to dr delay t crd dclk , dr pin 415 416 417 m s 12 3-wire interface timming (mode 1) frequency f dclk1 -- -- 1 mhz duty cycle 30 -- 70 % risetime t r1 dclk pin -- -- 20 ns rate t dds 500 -- -- ns input fsk to data delay t ddh dclk , dr pin 500 -- -- ns a. dbv= decibels above or below a reference voltage of 1vrms. signal level is per tone. b. dbm = decibels above or below a reference power of 1mw into 600 ohms. 0dbm = 0.7746vrms. signal level is per tone. c. twist = 20 log (f h amplitude / f l amplitude). notes: 1. both tones have the same amplitude. 2. band limited random noise 300-3400hz. measurement valid only when tone is present. 3. with gain setting as shown in figure 10. production tested at v dd =3v 10%, 5v 10%. 4. range within which tones are accepted. 5. ranges outside of which tones are rejected. 6. both mark and space have the same amplitude. 7. band limited random noise (200-3400hz). present when fsk signal is present. note that the bt band is 300-3400hz, the bellcore band is 0-4khz. 8. production tested at v dd =5v 10%, 3v 10%. 9. refer to figure 16 and 19. 10. into 50pf load. 11. fsk input data at 1200 12 baud. 12. osci at 3.579545 mhz 0.1%. 13. function of signal condition.
silan semiconductors SC88E43 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2000.12.31 7 pin description pin no. symbol i/o function 1 in+ input non-inverting input of the internal opamp. 2 in- input inverting input of the internal opamp. 3 gs output gain select of internal opamp. the opamps gain should be set according to the nominal vdd of the application using the information in figure 10. 4v ref output reference voltage. nominally vdd/2. it is used to bias the input opamp. 5cap -- capacitor. a 0. 1 mf decoupling capacitor should be connected across this pin and v ss. 6 trigin trigger input trigger input. schmitt trigger buffer input. used for line reversal and ring detection. 7 trigrc open drain output / schmitt input trigger rc. used to set the (rc) time interval from trigin going low to trigout going high. an external resistor connected to v dd and capacitor connected to v ss determine the duration of the (rc) time interval. 8 trigout cmos output trigger out. schmitt trigger buffer output. used to indicate detection of line reversal and/or ringing. 9 mode cmos input 3-wire interface: mode select. when low, selects fsk data interface mode 0. when high, selects fsk data interface mode 1. see pin 16 (dclk) description to understand how mode affects the dclk pin. 10 osci input oscillator input. a 3.579545mhz crystal should be connected between this pin and osco. it may also be driven directly from an external clock source. 11 osco output oscillator output. a 3.579545mhz crystal should be connected between this pin and osci. when osci is driven by an external clock, this pin should be left open. 12 vss -- power supply ground. 13 ic -- internal connection. must be connected to v ss for normal operation. 14 pwdn schmitt input power down. active high. when high, the device consumes minimal power by disabling all functionality except trigin, trigrc and. trigout must be pulled low for device operation. (to be continued)
silan semiconductors SC88E43 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2000.12.31 8 (continued) pin no. symbol i/o function 15 fsken cmos input fsk enable. must be high for fsk demodulation. this pin should be set low to prevent the fsk demodulator from reacting to extraneous signals (such as speech, alert signal and dtmf which are all in the same frequency band as fsk). 16 dclk cmos input/output 3-wire interface: data clock. in mode 0 (mode pin low), this pin is an output. in mode 1 (mode pin high), this pin is an input. 17 data cmos output 3-wire interface: data. in mode 0 the fsk data appears at the pin once demodulated. in mode 1 the fsk data is shifted out on the rising edge of the microcontroller supplied dclk. 18 dr cmos output 3-wire interface: data ready. active low. in mode 0 this output goes low after the last dclk pulse of each data word. this identifies the 8- bit word boundary on the serial output stream. typically, dr is used to latch 8-bit words from a serial-to-parallel converter into a microcontroller. in mode 1 this pin will signal the availability of data. 19 cd cmos output carrier detect. active low. a logic low indicates the presence of in- band signal at the output of the fsk bandpass filter. 20 int open drain output interrupt. active low. it is active when trigout or dr is low, or std is high. this output stays low until all three signals have become inactive. 21 std cmos output dual tone alert signal delayed steering output. when high, it indicates that a guard time qualified alert signal has been detected. 22 est cmos output dual tone alert signal early steering output. alert signal detection output. used in conjunction with st/gt and external circuitry to implement the detect and non-detect guard times. 23 st/gt analog input / cmos output dual tone alert signal steering input/guard time. a voltage greater than v tgt (see figure 4) at the st/gt pin causes the device to indicate that a dual tone has been detected by asserting std high. a voltage less than v tgt frees the device to accept a new dual tone. 24 v dd -- positive power supply.
silan semiconductors SC88E43 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2000.12.31 9 functional description detection of clip/cid call arrival indicators the cricuit in figure 3 illustrates the relationship between the trigrc and trigout sig nals.tpically,the three pin combination is used to detect an event indicated by an increase of the trigin voltage from v ss to above the schmitt trigger high going threshold v t+ (see dc electrical characteristics). figure 3 shows a circuit to detect any one of three clip/cid call arrival indicators:line reversal,ring burst and ringing. to determine values for c3 and r5: r5c3=-t/ln(1-v trigrc /v dd ) max vt+=0.68 v dd min v t+ =0.48 v dd v dd SC88E43 trigin trigrc trigout c3=220nf r5=150k r3=200k r4=310k r1=499k r2=499k v1 v3 v4 c2=100nf c1=100nf tip/a ring/b to microcontroller notes: the application circuit must ensure rhat, v trigin >max v t+ where max v t+ =3.74v @v dd =5.5v. tolerance to noise between a/b and v ss is: max vnoise=(min v t+ )/0.30+0.7=5.6vrms@4.5vv dd suggested r5c3 component values: r5 from 10k to 500k ; c3 from 47nf to 0.68 f an example is c3=220nf, r5=150k ; trigout low from 21.6ms to 37.6ms after trigin signal stops triggering the circuit. figure 3 circuit to detect line reversal, ring burst and ringing 1.line reversal detection line reversal,or polarity reversal on the a and b wires indicates the arrival of an inconming cdscall,as soecified in sin227.when the event (line reversal) occurs,trigin rises past the high going schmitt threshold v t+ and t trigou ,which is normally high,is pulled low going schmitt threshold v t- and trigout returns high.the components r5 and c3 (see figure 3) at trigout low interval. in a te designed for clip,the trigout high to low transition may be used to interrupt or wake-up the micro- controller.the controller can thus be put into power-down mode to conserve power in a battery operater te. 2.ring buost detection cca doesnot support the dual tone alert signal (refer to dual tone alert single burst og ringing (duration 200- 450ms) that precedes clipfsk data.the ring burst may vary fron 30 to 75vrms and is approximately 25hz. again in atedesigned for cca clip ,the t trigou high to low reansition may be used to interrupt or wake-up the microcontroller.the controller can thus be put into power-down mode to conserve powerin a battery operated te.
silan semiconductors SC88E43 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2000.12.31 10 3.ring detection in bellcores cnd/cnam scheme, the cid fsk data is transmitted between the first and second ringing cycles. the circuit in figure 3 will generate a ring envelope signal (active low) at trigout for a ring voltage of at least 40vrms. r5 and c3 filter the ring signal to provide an envelope output. the diode bridge shown in figure 3 works for both single ended and balanced ringing. a fraction of the ring voltage is applied to the trigin input. when the voltage at trigin is above the schmitt trigger high going threshold v t+ , trigrc is pulled low as c3 discharges. trigout stays low as long as the c3 voltage stays below the minimum v t+ . in a cpe designed for cnd/cnam, the trigout high to low transition may be used to interrupt or wake up the microcontroller. the controller can thus be put into power down mode to conserve power. if precise ring duration determination is critical, capacitor c3 in figure 3 may be removed. the microcontroller will now be able to time the ring duration directly. the result will be that trigout will be low only as long as the ringing signal is present.previously the rc time constant would cause only one interrupt. dual tone alert signal detection the bt on hook (idle state) caller id scheme uses a dual tone alert signal whose characteristics are shown in table 1. bellcore specifications for a similar dual tone signal called cpe alerting signal (cas) for use in off-hook data transmission. for the cidcw service, the cas must be detected in the presence of near end speech. the cas detector must also be immune to imitation from near and farend speech. item bt bellcore low tone frequency 2130hz 1.1% 2130hz 0.5% high tone frequency 2750hz 1.1% 2750hz 0.5% received signal level -2dbv to C40dbv per tone on- hook a (0.22dbm b to C37.78dbm) -14dbm b to C32dbm per tone on-hook signal reject level -46dbv (-43.78dbm) -45dbm signal level differntial (twist) up to 7db up to 6db unwanted signals -20db(300-3400hz) C7dbm asl c near end speech duration 88ms to 110ms d 75ms to 85ms speech present no yes table 1 dual tone alert signal characteristics a. in the future bt may specify the off-hook signal level as C15dbm to C34dbm per tone for bt cidcw. b. the signal power is expressed in dbm referenced to 600 ohm at the cpe a/b (tip/ring) interface. c. asl = active speech level expressed in dbm referenced to 600 ohm at the cpe tip/ring interface. the level is measured according to method b of recommendation p.56 "objective measurement of active speech level" published in the ccitt blue book, volume v "telephone transmission quality" 1989. epl (equivalent peak level) = asl+11.7db. d. sin227 suggests that the recognition time should be not less than 20ms if both tones are detected.
silan semiconductors SC88E43 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2000.12.31 11 in the SC88E43 the dual tone signal is separated into a high and a low tone by two bandpass filters. a detection algorithm examines the two filter outputs to determine the presence of a dual tone alert signal. the est pin goes high when both tones are present. note that est is only a preliminary indication. the indication must be sustained over the tone present guard time to be considered valid. tone present and tone absent guard times can be implemented with external rc components. the tone present guard time rejects signals of insufficient duration. the tone absent guard time masks momentary detection dropout once the tone present guard time has been satisfied. std is the guard time qualified detector output. dual tone detection guard time when the dual tone signal is detected by the SC88E43, est goes high. when the signal ceases to be detected, est goes low. the est pin indicates raw detection of the dual tone signal. since the bt application requires a minimum signal duration and the bellcore application requires protection from imitation by speech, est detection must be guard time qualified. the std pin provides guard time qualified signal detection. when the SC88E43 is used in a caller identity system, std indicates correct cas/tone alert signal detection. + - b a sw1 r c est std st/gt vdd p n q1 q2 vss =vss v tgt comparator from detector tone detected SC88E43 figure 4 : guard time circuit operation figure 4 shows the relationship between the st/gt, est and std pins. it also shows the operation of the guard time circuit. the total recognition time is t rec =t gp +t dp , where t gp is the tone present guard time and t dp is the tone present detect time (refer to timing between est, st/gt and std in figures 17 and 20). the total tone absent time is t abs =t ga +t da , where t ga is the tone absent guard time and t da is the tone absent detect time (refer to timing between est, st/gt and std in figures 17 and 20). bellcore states that it is desirable to be able to turn off cas detection for an off-hook capable cpe. the disable switch allows the subscriber who disconnects a service that relies on cas detection (e.g., cidcw) but retains the cpe, to turn off the detector and not be bothered by false detection. when sw1 in figure 4 is in the b position the guard time circuit is disabled. the detector will still process cas/alerting tones but the SC88E43 will not signal their presence by ensuring that std is low. bt specifies that the idle state tone alert signal recognition time should not be less than 20ms when both tones are used for detection. that is, both tones must be detected together for at least 20ms before the signal can be declared valid. this requirement can be met by setting the t gp (refer to figure 5) to at least 20ms.
silan semiconductors SC88E43 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2000.12.31 12 bt also specifies that the te is required to apply a dc wetting pulse and an ac load 15-25ms after the end of the alerting signal. if t abs =t da +t ga is 15 to 25ms, the dc current wetting pulse and the ac load can both be applied at the falling edge of std. the maximum t da is 8ms so t ga should be 15-17ms. therefore, t gp must be greater than t ga . figure 5(a) shows a possible implementation. the values in figures 9 and 11 (r2=r3=422k, c=0.1mf) will meet the bt timing requirements. 24 23 22 v dd st/gt est c r1 r2 v d =diode forward voltage SC88E43 (a) t gp >t ga t gp =r1cln[v dd /(v dd -v tg )] t ga =rpcln[(v dd -v d (rp/r2))/(v tgt -v d (rp/r2))] rp=r1r2/(r1+r2) 24 23 22 v dd st/gt est c r1 r2 v d =diode forward voltage SC88E43 (b) t gp SC88E43 provides an input arrangement comprised of an operational amplifier, and a bias source (vref ) which is used to bias the opamp inputs at v dd /2. the feedback resistor at the opamp output (gs) can be used to adjust the gain. in a single-ended configuration, the opamp is connected as shown in figure 6. for a differential input configuration, figure 7 shows the necessary connections. 3 2 1 4 cr in r f in+ gs in- v ref voltage gain (a v )=r f /r in figure 6 single ended input configuration 3 2 1 4 c r 4 in+ gs in- v ref differental input amplifler c1=c2 r1r4 (for unity gain r5=r4) r3=(r2r5)/(r2+r5) voltage gain (avdiff)=r5/r1 (see figure 9,10,11) input impedance (zindiff)=2r1 2 +(1/c) 2 cr 1 r 2 r 3 r 5 figure 7 differential input configuration
silan semiconductors SC88E43 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2000.12.31 13 fsk demodulation the SC88E43 first bandpass filters and then demodulates the fsk signal. the carrier detector provides an indication of the presence of signal at the bandpass filter output. the SC88E43s dual mode 3-wire interface allows convenient extraction of the 8-bit data words in the demodulated fsk bit stream. note that signals such as cas/tone alert signal, speech and dtmf tones lie in the same frequency band as fsk. they will, therefore, be demodulated and as a result, false data will be generated. to avoid demodulation of false data, an fsken pin is provided so that the fsk demodulator may be disabled when fsk signal is not expected. there are two events that if either is true, should be used to disable fsken. the events are cd returning high or receiving all the data indicated by the message length word. item bt bellcore mark frequency (logic 1) 1300hz 1.5% 1200hz 1% space frequency (logic 0) 2100hz 1.5% 2200hz 1% received signal level-mark -8dbv to C40dbv (-5.78dbm to C37.78dbm) -12dbm a to C32dbm received signal level-space -8dbv to C40dbv -12dbm to C36dbm signal level differntial (twist) up to 6db up to 10db b unwanted signals -20db (300-3400hz) C25dbm (0-4khz) c transmission rate 1200baud 1% 1200baud 1% word formate 1 start bit (logic 0), 8 bit word (lnb first), 1 to 10 stop bits (logic 1) 1 start bit (logic 0), 8 bit word (lnb first), 1 stop bits (logic 1) table 2 fsk charateristics a.the signal power is expressed in abm referenced to 600 w at the cpe tip/ring (a/b) interface. b.sr-3004, issue 2, january 1995. c.the frequency range is specified in gr-30-core. d.up to 20 marks may be inserted in specific places in a single or multiple data message. the fsk characteristics described in table 2 shows the bt and bellcore specifications. the bt frequencies correspond to ccitt v.23. the bellcore frequencies correspond to bell 202. the u.k.s cca requires that the te be able to receive both ccitt v.23 and bell 202 formats. the SC88E43 is compatible with both formats without any adjustment. 3-wire fsk data interface the SC88E43 provides a powerful dual mode 3-wire interface so that the 8-bit data words in the demodulated fsk bit stream can be extracted without the need either for an external uart or for the te/cpes microcontroller to perform the uart function in software. the interface is specifically designed for the 1200 baud rate and is comprised of the data, dclk (data clock) and dr (data ready) pins. two modes (modes 0 and 1) are selectable via control of the devices mode pin: in mode 0, data transfer is initiated by the SC88E43; in mode 1, data transfer is initiated by the external microcontroller.
silan semiconductors SC88E43 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2000.12.31 14 mode 0 this mode is selected when the mode pin is low. in this mode, the SC88E43 receives the fsk signal, demodulates it, and outputs the data directly to the data pin (refer to figure 14). for each received stop and start bit sequence, the SC88E43 outputs a fixed frequency clock string of 8 pulses at the dclk pin. each clock rising edge occurs in the centre of each data bit cell. dclk is not generated for the stop and start bits. consequently, dclk will clock only valid data into a peripheral device such as a serial to parallel shift register or a micro-controller. the SC88E43 also outputs an end of word pulse (data ready) on the dr pin. the data ready signal indicates the reception of every 10-bit word (including start and stop bits) sent from the network to the te/cpe. this dr signal can be used to interrupt a micro-controller. dr can also cause a serial to parallel converter to parallel load its data into a microcontroller. the mode 0 data pin can also be connected to a personal computers serial communication port after converting from cmos to rs-232 voltage levels. mode 1 this mode is selected when the mode pin is high. in this mode, the microcontroller supplies read pulses (dclk) to shift the 8-bit data words out of the SC88E43, onto the data pin. the SC88E43 asserts dr to denote the word boundary and indicate to the microprocessor that a new word has become available (refer to figure 16). internal to the SC88E43, the demodulated data bits are sampled and stored. after the 8th bit, the word is parallel loaded into an 8 bit shift register and dr goes low. the shift registers contents are shifted out to the data pin on the supplied dclks rising edge in the order they were received. if dclk begins while dr is low, dr will return to high upon the first dclk. this feature allows the associated interrupt (see section on "interrupt") to be cleared by the first read pulse. otherwise dr is low for half a nominal bit time (1/2400 sec). after the last bit has been read, additional dclks are ignored. carrier detector the carrier detector provides an indication of the presence of a signal in the fsk frequency band. it detects the presence of a signal of sufficient amplitude at the output of the fsk bandpass filter. the signal is qualified by a digital algorithm before the cd output is set low to indicate carrier detection. an 8ms hysteresis is provided to allow for momentary signal drop out once cd has been activated. cd is released when there is no activity at the fsk bandpass filter output for 8 ms. when cd is inactive (high), the raw output of the demodulator is ignored by the data timing recovery circuit (refer to figure 1). in mode 0, the data pin is forced high. no dclk or dr signal is generated. in mode 1, the internal shift register is not updated. no dr is generated. if the mode 1 dclk is clocked, data is undefined. note that signals such as cas/tone alert signal, speech and dtmf tones also lie in the fsk frequency band and the carrier detector may be activated by these signals. the signals will be demodulated and presented as data. to avoid false data detection, the fsken pin should be used to disable the fsk demodulator when no fsk signal is expected. ringing, on the other hand, does not pose a problem as it is ignored by the carrier detector.
silan semiconductors SC88E43 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2000.12.31 15 interrupt to facilitate interfacing with microcontrollers running interrupt driven firmware, an open drain interrupt output int is provided. int is asserted when trigout is low, std is high, or dr is low. when int is asserted, these signals should be read (into an input port of the microcontroller) to determine the cause of the interrupt ( trigout , std or dr ) so that the appropriate response can be made. when system power is first applied, trigout will be low because capacitor c3 at trigrc (see figure 3) has no initial charge. this will result in an interrupt upon power up. also when system power is first applied and the pwdn pin is low, an interrupt will occur due to std. since there is no charge across the capacitor at the st/gt pin in figure 4, std will be high triggering an interrupt. the interrupts will not clear until both capacitors are charged. the microcontroller should ignore interrupt from these msources on initial power up until there is sufficient time to charge the capacitors. it is possible to clear std and its interrupt by asserting pwdn immediately after system power up. when pwdn is high, std is low. pwdn will also force both est and the comparator output low, q2 will turn on so that the capacitor at the st/gt pin charges up quickly (refer to figure 4). power down mode for applications requiring reduced power consumption, the SC88E43 can be powered up only when it is required, that is, upon detection of one of three clip/cid call arrival indicators: line reversal, ring burst and ringing. the SC88E43 is powered down by setting the pwdn pin to logic high. in power down mode, the oscillator, input opamp and all internal circuitry are disabled except for trigin, trigrc and t trigou pins. these three pins are not affected by power down, such that, the SC88E43 can still react to call arrival indicators. the SC88E43 can be powered up by setting the pwdn pin to logic low. crystal oscillator the SC88E43 requires a 3.579545mhz crystal oscillator as the master timing source. 10 11 osci osco SC88E43 3.579545 mhz 10 11 osci osco SC88E43 10 11 osci osco SC88E43 to the next SC88E43 figure 8 common crystal connection the crystal specification is as follows : frequency: 3.579545 mhz frequency tolerance: 0.1%(-40 o c+85 o c) resonance mode: parallel load capacitance: 18 pf maximum series resistance: 150 ohms maximum drive level (mw): 2 mw any number of SC88E43 devices can be connected as shown in figure 8 such that only one crystal is required. the connection between osc2 and osc1 can be dc coupled as shown, or the osc1 input on all devices can be driven from a cmos buffer (dc coupled) with the osc2 outputs left unconnected. to meet bt and bellcore requirements for proper tone detection the crystal must have a frequency tolerance of 0.1%.
silan semiconductors SC88E43 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2000.12.31 16 vref and cap inputs v ref is the output of a low impedance voltage source equal to v dd /2 and is used to bias the input opamp. a 0.1mf capacitor is required between cap and v ss to eliminate noise on v ref. SC88E43 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 in+ in- gs vref cap v ss mode st/gt est std data dclk fsken pwdn ic v dd int oscout oscin trigin cd dr trigrc trigout v dd 499k 5% 1n914 x 4 100nf 5% 499k 5% 100nf 5% 200k 5% 301k 5% 22nf 5% 22nf 5% 1n4003 1n4003 1n4003 1n4003 r1 r1 tip /a ring / b v dd v dd v dd 150k 5% 220nf 100nf tisp 4180 r4 r4 464k 464k 53k6 60k4 r3 1n914 r2 v dd v dd 100nf 100k 20% c note:resistors must have 1% tolerance and capacitors have 20% tolerance unless otherwise specified. crystal is 3.579545mhz, 0.1% frequency tolerance. for bt application c=0.1 f 5%, r3=422k 1%, r2=422k 1%. for applications where cas speech immunity is required(e.g.cidcw), c=0.1 f 5%, r3=825k 1%, r2=226k 1%. r1=430k, r4=34k for vdd=5v 10% (see figure 10) r1=620k, r4=63k4 for vdd=3v 10% (see figure 10) figure 9- application circuit application circuits the circuits shown in figures 9 and 11 are application circuits for the SC88E43. as supply voltage (vdd ) is decreased, the threshold of the devices tone and fsk detectors will be reduced. therefore, to meet the bt or bellcore tone reject level requirements the gain of the input opamp should be reduced according to the graph in
silan semiconductors SC88E43 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2000.12.31 17 figure 10. for example when vdd =5v (+/- 10%), r 1 should equal 430kw and r4 should equal 34kw; and if vdd =3v (+/- 10%) r1 should equal 620kw and r 4 should equal 63.4kw. resistors r1 and r4 are shown in figures 9 and 11. the circuit shown in figure 9 illustrates the use of the SC88E43 in a proprietary system that doesnt need to meet fcc, doc, and ul approvals. it should be noted that if glitches on the tip/ring interface are of sufficient amplitude, the circuit will falsely detect these signals as ringing or line reversal. the circuit shown in figure 11 will provide common mode rejection of signals received by the ringing circuit. this circuit should pass safety related tests specified by fcc part 68, doc cs-03, ul 1459, and csa c22.2. these safety tests will simulate high voltage faults that may occur on the line. the circuit provides isolation from these high voltage faults via r1 and the 12.1kw resistors as well as the 22nf & 330nf capacitors. irc manufactures a resistor (part number gs3) that should be used for r1. this resistor is a 3w, 5%, 1kv power resistor. the 12k1 resistor is manufactured by irc (part number fa8425f). this resistor is a 1.5w, 5%, fuseable type resistor. the 22nf and 330nf capacitors have a 400v rating. 1 0.95 0.9 0.85 0.8 0.75 0.7 0.65 0.6 gain ratio 22.533.544.555.56 nominal v dd (volts) 0.678 figure 10: gain ratio as a function of nominal v dd note: in the application circuits shown in figure9 and 11, the gain ratio of SC88E43 opamp is: gain ratio=464k /(r1+r4)
silan semiconductors SC88E43 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2000.12.31 18 SC88E43 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 in+ in- gs vref cap v ss mode st/gt est std data dclk fsken pwdn ic v dd int oscout oscin trigin cd dr trigrc trigout v dd 22nf 5% 22nf 5% 1n4003 1n4003 1n4003 1n4003 r1 r1 tip /a ring / b v dd v dd v dd 150k 5% 100nf tisp 4180 r4 r4 464k 53k6 60k4 r3 1n914 r2 v dd v dd 100nf 100k 20% c v dd 220nf 10nf 200k 5% 464k 5% 4n25 12k1 5% 330nf 10% 100nf 10% 1n914 x 4 1n5231b note: please use 0.068 m f, 1500pf mylar capacitors. note:resistors must have 1% tolerance and capacitors have 20% tolerance unless otherwise specified. crystal is 3.579545mhz, 0.1% frequency tolerance. for bt application c=0.1 f 5%, r3=422k 1%, r2=422k 1%. for applications where cas speech immunity is required(e.g.cidcw), c=0.1 f 5%, r3=825k 1%, r2=226k 1%. r1=430k, r4=34k for vdd=5v 10% (see figure 10) r1=620k, r4=63k4 for vdd=3v 10% (see figure 10) figure 11:application circuit with improved common mode noise immunity and isolation in line interface approvals fcc part 68,doc cs-03,ul1459,and can/csa-22.2 no.225-m90 are all system(i.e. connectors,power supply,cabinet,ect.) requirements. since the SC88E43 is a component and not a system, the application circuit (figure 11) has been designed to meet the co trunk interface requirments of fcc,doc,ul, and csa; thus enabling the complete system to be approved by these standards bodies.
silan semiconductors SC88E43 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2000.12.31 19 v hm v ct v lm v hm v ct v lm t cdd t f t f t r t ch t cl t r t dcd data dclk figure 12: data and dclk mode 0 output timing v hm v ct v lm t rr t rl t rf dr figure 13: dr output timing b7 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1 0 b0 b1 b2 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 t rl t crd 1/f dclc0 stop stop stop start start start t idd stop start stop start stop start tip/ring (a/b) wires data dclk dr figure 14: serial data interface timing (mode 0)
silan semiconductors SC88E43 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2000.12.31 20 v hm v ct v lm t r1 dclk figure 15: dclk mode 1 input timing 7 demodulated internal bit stream data dclk dr stop start 0 1 2 3 4 5 6 7 stop 67 01234567 0 word n word n-1 t dds t ddh 1/f dclk1 t rl word n word n+1 1 2 1 2 dclk clears dr dclk does not clear dr ,sodr is low for maximum time (1/2 bit width) figure 16: serial data interface timing (mode 1)
silan semiconductors SC88E43 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2000.12.31 21 a/b wires std pwdn trigout t dp est st/gt te dc load te ac load fsken cd dr dclk data oscout 101010 data line reversal alerting signal ch.seizure mark data packet ring note 6 ab c d e f g t da t gp t rec t ga v tgt t abs note 3 note 2 note 1 50--150ms 15+/-1ms <120ua 20+/-5ms current wetting pulse (see sin227) <0.5ma (optional) zss (refer to sin227) note 4 note 5 t cp t pd t pu a>=100ms b=88--110ms c>=45ms (up to 5sec) d=80--262ms e=45--75ms f<=2.5s (typ.500ms) g>200ms note: all values obtained from sin227 issue 1 t ca figure 17: input and output timing for bt caller display service(cds), e.g.,clip note: 1) the total recognition time is t rec =t gp +t dr ,where t gp isthetonepresentguardtimeandt dp is the tone present detect time (refer to section dual tone detection time on page 11 for details). v tgt is the comparator threshold (refer to figure 4). 2) the total tone absent time is t abs =t ga +t da , where tga is the tone absent guard time and t da is the tone absent detect time (refer to section dual tone detection time on page 11 for details). v tgt is the comparator threshold (refer to figure 4). 3) by choosing t ga =15ms, t abs will be 1525 ms so that the current wetting pulse and ac load can be applied right after the std falling edge. 4) sin227 spedifies that the ac and dc loads should be removed between 50150 ms after the end of the fsk signal, indicated by cd returning to high. the SC88E43 may also be powered down at this time. 5) fsken should be set low when fsk is not expected to prevent the fsk demodulator from reacting to other in-band signals such as speech, tone alert signal and dtmf tones. 6) t trigou is the ring envelope during ringing.
silan semiconductors SC88E43 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2000.12.31 22 a/b wires pwdn trigout te dc load te ac load fsken cd dr dclk data oscout 101010 data line reversal ring burst ch.seizure mark data packet first ring cycle abcde note 1 note 2 t cp t pd t pu a=200-450ms b>=500ms c=80--262ms d=45--262ms e<=2.5s (type. 500ms) f>200ms note: parameter f from " cca exceptions document issue 3" t ca 250--400ms f 50--150ms note 3 note 3 figure 18: input and output timing for cca caller display service(cds), e.g.,clip note: 1. tw/p&e/312 specifies that the ac and dc loads should be removed between 50 to 150 ms after the end of the fsk signal, indicated by the cd returning to high. the SC88E43 may also be powered down at this time. 2. fsken should be set low when fsk is not expected to prevent the fsk demodulator from reacting to other in-band signals such as speech,and dtmf tones. 3. t trigou represents the ring envelop during ringing.
silan semiconductors SC88E43 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2000.12.31 23 a/b wires pwdn trigout fsken cd dr dclk data oscout 101010 data ch.seizure mark data packet ab c d e t cp t pd t pu a=2 sec typical b=250--500ms c=250ms d=150ms e=feature specific max c+d+e=2.9 to 3.7 sec t ca f 2nd ring note 3 note 1 note 4 f>=200ms 1st ring note 1 note 2 figure 19: input and output timing for bellcore on-hook data transmission associated with ringing,e.g.,cid note: this on-hook case application is included because a cidcw (off-hook) cpe should also be capable of receiving on-hook data transmission (with ringring) from the end office. tr-nwt-000575 specifies that cidcw will be offered only to lines which subscribe to cid 1. the cpe designer may choose to enable the SC88E43 only after the end of ringing to conserve power in a battery operated cpe. cd is not activated by ringing. 2. the cpe designer may choose to set fsken always high while the cpe is on-hook. setting fsken low prevents the fsk demodulator from reacting to other in-band signals such as speech,cas or dtmf tones. 3. the microcontroller in the cpe powers down the SC88E43 after cd has become inactive. 4. the microcontroller times out if cd is not activated.
silan semiconductors SC88E43 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2000.12.31 24 a/b wires std pwdn t dp est st/gt fsken cd dr dclk data oscout data cpe goes off-hook mark abcde g t da t gp t rec t ga v tgt t abs cas note 1 t cp t pu a=75--85ms b=0--100ms c=55--65ms d=0-500ms e=58--75ms f=feature specific g<50ms f (note 6) note 7 note 8 t ca t cp note 5 note 3 note 4 note 2 cpe mutes hangset & disables keypad ack cpe sends data packet cpe unmutes handset and enables keypad figure 20: input and output timing for bellcore off-hook data transmission,e.g., cidcw note: 1. in a cpe where ac power is not available, the designer may choose to switch over to line power when the cpe goes off-hook and use battery power while on-hook. the cpe should also be cid (on-hook) capable because tr-nwt-000575 specifies that cidcw will be offered only to lines which subscribe to cid. 2. non-fsk signals such as cas, speech and dtmf tones are in the same frequency band as fsk. they will be demodulated and give false data. the fsken pin should be set low to disable the fsk demodulator when fsk is not expected. 3. fsken may be set high as soon as the cpe has finished sending the acknowledgment signal ack. tr-nwt-000575 specifies that ack=dtmf d for non-adsi cpe, a for adsi cpe. 4. fsken should be set low when cd has become inactive. 5. in an unsuccessful attempt where the end office does not send the fsk signal, the cpe should unmute the handset and enable the keypad after this interval. 6. sr-tsv-002476 states that it is desirable that the cpe have an on/off switch for the cas detector. see sw1 in figure 4. 7. the total recognition time is t rec =t gp +t dr ,where t gp isthetonepresentguardtimeandt dp is the tone present detect time (refer to section dual tone detection time on page 11 for details). v tgt is the comparator threshold (refer to figure 4). 8. the total tone absent time is t abs =t ga +t da , where tga is the tone absent guard time and t da is the tone absent detect time (refer to section dual tone detection time on page 11 for details). v tgt is the comparator threshold (refer to figure 4).
silan semiconductors SC88E43 hangzhou silan microelectronics joint-stock co.,ltd rev: 1.0 2000.12.31 25 package outline dip-24-600-2.54 unit:mm 13.60 3.85 15.24 0.25 15 degree 0.46 32.04 2.54 1.50 5.08 3.30 sop-24-375-1.27 unit:mm 10.45 7.70 9.53 1.95 15.74 15.34 1.27 0.41

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